There are generally two classes of previous data processors with respect to the subject of structural configuration of address and data buses of a data processing system. A first class of data processing system bus structures includes data processing systems which have separate and distinct address and data buses and which always communicate bits independent of each other. A second class of data processing system includes data processors having address and data bits multiplexed and communicated via the same communication bus. Of the second class of data processing systems, two sub-classes of data processors typically exist. A first sub-class of data processors includes data processors which have separate and distinct paths and architectures for data and address bits. Multiplexing of address and data bits in a data processing system for this sub-class of data processors is implemented by a multiplexor and control circuitry external to the data processor integrated circuit chip. Therefore, a circuit board size penalty exists for this sub-class of data processors in order to obtain a multiplexed data and address bus. Also, inherent delay, particularly set-up time for the multiplexing circuitry external to the integrated circuit data processor, generally slows system operating speeds and performance. A second sub-class of data processors includes data processors which internally multiplex data and address buses onto a single external communication bus. A disadvantage with this sub-class of data processors is that the data processor always has a multiplexed bus operation and a specific bus protocol giving a user no system flexibility to modify this system feature. Because previous data processors have not allowed a user equally satisfactory system performance with respect to the choice of multiplexing of address and data bus structures, designers have previously had to use a specific type of data processor in response to the bus structure chosen or have otherwise suffered a performance penalty resulting from circuit delay associated with multiplexing circuitry contained on a single integrated circuit chip.